#615 overall
Computation Structures Part 2: Computer Architecture
edX
1 recommender · 2 threads · recommended in 2 years, 2016–2019 · score 0.8
The second part of MIT's Computation Structures sequence on edX, covering instruction set architectures and assembly, stacks and procedures, 32-bit computer architecture, the memory hierarchy, and caches. Students design and implement a 32-bit RISC CPU at the gate level in a browser-based simulator, with memory provided as a black box.
Commenters present it as the follow-on to Part 1 that takes you from a working ALU to a full processor, and one who took it says it is worth the time.
CS Fundamentals & Systemsintermediatefreeinteractive MOOC#computer architecture#cpu design#digital logic#caches#risc#edx
Recommendations by year
20062026
A whole lot of people know how to make a CPU. It's not as hard as you probably think it is. What's hard is making them as complex, fast, and small as we do nowadays. But if you can get by with something not as complex or fast, and that takes up most of your desk, thousands of people know how to do it.
Got 120 hours and want to become one of them? Take these two courses from EdX, which are 60 hours each:
"Computation Structures - Part 1: Digital Circuits" [1]
"Computation Structures 2: Computer Architecture" [2]
The first teaches "[...] digital encoding of information, principles of digital signaling; combinational and sequential logic, implementation in CMOS, useful canonical forms, synthesis; latency, throughput and pipelining". In the homework and labs you design and implement (in a simulator) a 32-bit ALU.
The second covers "[...] instruction set architectures and assembly language, stacks and procedures, 32-bit computer architecture, the memory hierarchy, and caches". In the homework and labs you design and implement (in a simulator) at the gate level a 32-bit RISC CPU, except for memory. Memory for registers and program is given as a black box--by this point you know enough to design that, but it would just add a lot of components and complexity, and slow down the simulation, and the time spent dealing with it would distract from learning the topic of this part of the course. That would fit better with the first part of the course.
I've taken these, and can say they do a good job of teaching what they say they teach.
There's also a third course in the series:
"Computation Structures 3: Computer Organization" [3]
That covers "[...] pipelined computers, virtual memories, implementation of a simple time-sharing operating system, interrupts and real-time, and techniques for parallel processing".
In the homework and labs for that one, you optimize your CPU from the second part for size and speed, and make it support time sharing operating systems.
I've not taken this one.
[1] https://www.edx.org/course/computation-structures-part-1-dig...
[2] https://www.edx.org/course/computation-structures-2-computer...
[3] https://www.edx.org/course/computation-structures-3-computer...
For software people who find this interesting and would like a great introduction, consider taking the course "Computation Structures" from MITx on EdX.
It's in three parts. The next run of part I, "Digital Circuits", starts September 6th. Here's the link: https://www.edx.org/course/computation-structures-part-1-dig...
Part I cpvers basic logic gates, at both a high level (how you use them) and a lower level (how you build them on a chip), their characteristics (propagation delay, contamination delay, and things like that), combinatorial logic, sequential logic, state machines, pipelining, and probably more that I don't remember. The labs are done via a browser-based simulator, and by the end of the course you will have designed and implemented a 32-bit ALU with add, subtract, logical and arithmetic shifts in both directions by up to 31 bits, all the boolean operators, and the usual comparison operators.
Part II builds on that, taking you through designing and implementing a full 32-bit processor. Caching is discussed in the lectures, but not used in the processor.
Part III (which I did not have time to take), I believe, adds caching and pipelining to the processor, and covers parallel processing and device handling, and also operating system stuff.
For a while I wanted to actually build the processor from Part II using discrete 7400 series logic, but the chip count came in too high for me. My gate counts were: 295 AND2, 8 AND3, 3 NOR2, r OR2, 96 OR3, 20 OR4, 226 XOR2, 6 NOT, 563 MUX2, 161 MUX4. (That's not counting whatever I'd need for the control ROM and the 32 x 32-bit register file).
At 4 MUX2s per chip, and 4 AND2s per chip, that's 215 chips. Another 81 for the MUX4s and 57 for the XOR2s brings it up to 353. Without even tossing in the rest, I'm way over my limit.
I could cut this down quite a bit by taking out the shift unit (which uses 353 MUX2s), making the shift instructions generate an illegal instruction trap, and have the trap handler emulate the shift instructions. That would save 88 chips. (Well, not quite 88 chips...I think I'd have to add a "logical right shift by 1" instruction to make it so this approach would not be too slow, but a dedicated "logical right shift by 1" unit is a lot simpler than a "shift logical or arithmetic in any direction by any amount" unit).
The cool thing though, is that I, a software guy, could could actually make those hardware changes now. A lot of things about computers now make a lot more sense to me. I highly recommend it to those curious about what goes on at a lower level than we software guys normally deal with (even if we are writing software that interfaces with devices).